1. Field of the Invention
The present invention relates to a structure of a semiconductor integrated circuit device for supplying power supply potential to an internal circuit in a test mode operation mode. More specifically, the invention relates to a structure of a semiconductor integrated circuit device having a power supply circuit which supplies to an internal circuit an externally applied arbitrary voltage in a test mode.
2. Description of the Background Art
With the enhancement of integration of a semiconductor integrated circuit device such as dynamic random access memory (hereinafter referred to as DRAM), for example, it becomes necessary to ensure the reliability of a scaled down transistor which constitutes the circuit device and to simultaneously satisfy requirements of the specification of an interface for data communication with any external unit of the semiconductor integrated circuit.
In general, the semiconductor integrated circuit device such as semiconductor memory is accordingly provided with a voltage-down power supply circuit which lowers external power supply potential Ext.Vcc to generate internal power supply potential int.Vcc.
Additionally, in the DRAM, the reliability of a memory cell capacitor constituting a memory cell should be assured and further the circuit structure should be implemented with consideration of the noise resistance in data reading as well as low power consumption and guarantee of the read voltage margin. Therefore, in the DRAM, half of the internal power supply potential int.Vcc is supplied to a cell plate which is an electrode opposite to a storage node of the memory cell capacitor and half of the internal power supply potential int.Vcc is also supplied as the precharge potential of a bit line pair.
In addition, a negative potential (substrate potential) is supplied to the substrate for the purposes of improvement in the leakage current characteristic of the transistor, reduction in the parasitic capacitance and the like.
The DRAM thus generally has a plurality of internal power supply circuits placed therein such as voltage-down power supply circuit, cell plate voltage generation circuit, bit line precharge voltage generation circuit, substrate potential generation circuit and the like, even if the externally applied external power supply potential Ext.Vcc is a single potential of 3.3 V, for example.
Those internal power supply circuits are designed to generate a stable potential level even if external power supply potential Ext.Vcc varies so as to ensure the stable operation of internal circuits. Meanwhile, some operation tests of a device require confirmation of the operation state of the device which occurs when the internal power supply potential is intentionally changed in a certain range in order to confirm the operation margin of the device. However, in the structure discussed above which converts external power supply potential Ext.Vcc and applies the resultant potential to internal circuits via the internal power supply circuits mentioned above, it is difficult to externally set the potential level generated by the internal power supply circuits at a desired value.
Further, as a screening test before shipment of, for example, the DRAM, an accelerated test which is so-called burn-in test is conducted. The purpose of this test is to reveal potential failures in a memory cell capacitor, a gate insulating film of a transistor, multilayer interconnection and the like by operating the device under accelerated conditions such as high voltage, high environmental temperature and the like. In such an accelerated test, not the potential generated by the internal power supply circuits but any desired power supply potential should be applied to the internal circuits.
FIG. 9 is a schematic block diagram illustrating a structure of a conventional potential supply circuit 8000 which enables an externally supplied voltage to be applied to an internal circuit instead of voltage generated by an internal power supply circuit in a semiconductor integrated circuit device.
Referring to FIG. 9, potential supply circuit 8000 includes a test mode signal generation circuit 8010 which generates active test mode signal STEST according to a combination of a control signal and an address signal which are supplied from the outside of the DRAM, a voltage application circuit 8040 which connects an internal power supply node ns to a terminal 8020 receiving an externally applied supply potential in response to activation of test mode signal STEST and electrically disconnects internal power supply node ns from terminal 8020 when the test mode signal is in the inactive period, and an internal power supply voltage generation circuit 8030 which supplies internal power supply voltage int.V to internal power supply node ns when test mode signal STEST is in the inactive period and stops the operation when the test mode signal is in the active period.
Internal power supply voltage generation circuit 8030 in FIG. 9 represents any of the voltage-down power supply circuit, cell plate voltage generation circuit, bit line precharge voltage generation circuit, substrate potential generation circuit and the like.
The level of test mode signal STEST is herein at internal power supply voltage level int.Vcc in the active period and at ground potential level GND in the inactive period.
FIG. 10 is a circuit diagram illustrating a structure of voltage application circuit 8040 shown in FIG. 9.
Referring to FIG. 10, voltage application circuit 8040 includes an inverter INV500 operating at internal power supply voltage int.Vcc and receiving test mode signal STEST, a P channel MOS transistor P502 and an N channel MOS transistor N502 connected in series between external power supply voltage Ext.Vcc and ground potential GND, and a P channel MOS transistor P504 and an N channel MOS transistor N504 connected in series between external power supply voltage Ext.Vcc and ground potential GND.
Transistor N502 receives at its gate signal STEST and transistor N504 receives at its gate an output of inverter INV500. Transistor P504 has its gate coupled to a connection node n502 of transistors P502 and N502 and transistor P502 has its gate coupled to a connection node n504 of transistors P504 and N504.
Voltage application circuit 8040 further includes a P channel MOS transistor P506 and an N channel MOS transistor N506 connected in series between external power supply voltage Ext.Vcc and substrate potential Vbb which is a negative potential, and a P channel MOS transistor P508 and an N channel MOS transistor N508 connected in series between external power supply voltage Ext.Vcc and substrate potential Vbb.
The gate of transistor P506 is coupled to node n504 and the gate of transistor P508 is coupled to node n502. The gate of transistor N508 is coupled to a connection node n506 of transistors P506 and N506 and the gate of transistor N506 is coupled to a connection node n508 of transistors P508 and N508.
Voltage application circuit 8040 further includes an N channel MOS transistor N510 coupled between terminal 8020 and internal power supply node ns and having its gate potential controlled by the potential level of node n508.
An operation of voltage application circuit 8040 is now described briefly.
When test mode signal STEST attains an active state ("H" level: internal power supply voltage level int.Vcc), the output of inverter INV500 attains "L" level (ground potential level GND). In response to this, transistor N502 is set into the turn-on state while transistor N504 is set into the turn-off state.
Accordingly, the gate potential of transistor P504 is set at ground potential GND level by transistor N504 and transistor P504 attains the turn-on state. The potential level of node n504 then reaches external power supply voltage Ext.Vcc. On the other hand, transistor P502 remains in the turn-off state. The potential level of node n502 is thus at ground potential GND.
In response to change of the potential of node n504 to external power supply voltage Ext.Vcc, transistor P506 is turned off. In response to change of the potential of node n502 to ground potential GND, transistor P508 is turned on.
In response to change of the potential of node n508 to external power supply voltage Ext.Vcc, transistor N506 is turned on since the gate potential is at external power supply voltage Ext.Vcc. The potential level of node n506 is thus set at substrate potential Vbb of a negative potential. Transistor N508 is accordingly in the turn-off state.
Since the potential of node n508 attains external power supply voltage Ext.Vcc, transistor N510 is turned on to couple terminal 8020 to internal power supply node ns so that potential can be applied from terminal 8020 to internal power supply node ns.
On the other hand, when signal STEST is in an inactive state ("L" level: ground potential level), transistor N504 is turned on and transistor N502 is in turn-off state, so that transistor P502 is turned on and transistor P504 is set into the turn-off state. Accordingly, the level of node n502 attains external power supply voltage Ext.Vcc and the level of node n504 is set at the ground potential level.
This causes transistor P506 to be turned on and the potential of node n506 attains external power supply voltage Ext.Vcc. Accordingly, transistor N508 is turned on so that the potential of node n508, i.e. the gate potential of transistor N510 is set at substrate potential Vbb. Since transistor N510 is turned off, terminal 8020 is electrically disconnected from internal power supply node ns.
In other words, when signal STEST is in the active state, external power supply potential Ext.Vcc is applied to the gate of transistor N510, while substrate potential Vbb is applied thereto when signal STEST is in the inactive state. The external power supply voltage Ext.Vcc is applied to the gate of transistor N510 when test mode signal STEST is active in order to enable voltage of approximately internal power supply potential int.Vcc to be applied externally to internal power supply node ns via terminal 8020.
Substrate potential Vbb is applied to the gate of transistor N510 when test mode signal STEST is inactive so as to prevent undershoot applied to terminal 8020 from being transmitted to internal power supply node ns. However, if the threshold of transistor N510 is Vth and the magnitude of the undershoot is equal to or smaller than potential (Vbb-Vth), transistor N510 is turned on and the undershoot is transmitted to internal power supply node ns. If overshoot is applied to terminal 8020, transistor N510 in the turn-off state can maintain its turn-off state even if the overshoot is applied to terminal 8020 as transistor N510 is an N channel MOS transistor. Thus, the overshoot can be prevented from being applied to internal power supply node ns.
In potential supply circuit 8040 as shown in FIG. 10, when test mode signal STEST is active, voltage (.vertline.Ext.Vcc.vertline.+.vertline.Vbb.vertline.) is applied between the source and drain of transistors N508 and P506 and between the gate and source of transistor N506. When test mode signal STEST is inactive, voltage (.vertline.Ext.Vcc.vertline.+.vertline.Vbb.vertline.) is applied between the source and drain of transistors N506 and P508 and between the gate and source of transistor N508.
In recent years, the scale-down of semiconductor integrated circuit devices has been accompanied by reduction of the withstand voltage of a gate oxide film or the like. In particular, this problem is serious when a voltage like burn-in which is higher than that in the normal operation is applied to the transistor. It is not accordingly preferable in terms of the reliability that the relatively high voltage (.vertline.Ext.Vcc.vertline.+.vertline.Vbb.vertline.) is applied to the transistor.
This also means difficulty in application of a sufficiently high voltage externally to the internal circuits via terminal 8020 because of limitation of the transistor withstand voltage.